1. Field of the Invention
This invention is relates to a method of forming a gate structure, especially relates to a method of forming a gate structure used in borderless contact etching.
2. Description of the Prior Art
In the 0.3 .mu.m process, or below, used in fabricating dynamic random access memory (DRAM), the design rule is tightened due to the shrink of the contact window, and the bottle neck of exposure (I-line) is thus formed. In order to solve the problem aformentioned, the borderless contact etching process is developed.
The borderless contact etching process utilizes the etching-rate difference between two different materials to form a borderless contact, e.g., oxide to nitride, thus the borderless contact etching is achieved. The technique using borderless contact etching process is described below. Referring to FIG. 1A, the first step is to deposit a poly silicon layer 100 on a substrate 101, followed by depositing a silicon nitride layer 102 of 2000 angstroms in thickness.
The gate electrode 103 in FIG. 1B is formed by etching portions of layer 100 and layer 102. The etching process used to remove the portions of layer 100 and 102 is performed by conventional wet etching using a developed photoresist as a mask (not shown). Referring to FIG. 1C, to form a silicon nitride spacer, a layer composed of silicon nitride 104 of 1200 angstroms in thickness is formed by chemical vapor deposition on the surface of substrate 101 and gate electrode 103. The following step is to etch the silicon nitride layer 104 anisotropically to form the silicon nitride spacer 105 shown in FIG. 1D. The gate electrode and the spacers are thus formed. The following steps fabricating a DRAM is omitted. To make the metal interconnect, the contact window is formed by the following steps.
Deposit a silicon dioxide layer 106 on the topography of the wafer shown in FIG. 1E followed by etching the silicon dioxide layer 106 by an anisotropic etching to form a contact. The recipe used to make the contact is the mixture of C.sub.4 F.sub.8 /CO/Ar, the pressure is about 0.045 Torr and the power is about 1400 Watts. Due to the etching rate of the silicon dioxide is larger than that of the silicon nitride, the cross sectional view of the wafer is shown in FIG. 1E. The profile of the silicon nitride spacer 105 and the silicon nitride layer 102 shown in FIG. 1E is under the ideal condition. In fact, the silicon nitride loss in the corner of silicon nitride spacer 105 is more than that of the silicon nitride layer 102 of gate electrode 103, so the realistic cross sectional view of the wafer is shown in FIG. 1F.
To avoid the exposure of the poly silicon layer 100 during the etching step, the thickness of the silicon nitride spacer 105 must be thick enough, e.g., 2000 angstroms in thickness, to compensate the loss of the silicon nitride spacer 105. If the silicon nitride layer 102 were too thick, the step height will be worse because the thickness of the stack of the layers is increased. In addition, in the later section process, e.g., the 3C contact etching process, the control of etching is critical. The condition described above is shown in FIG. 2.
The multi-layer contact etching, etching the silicon dioxide 200 to contact first poly gate electrode 201, the bit line 202, the active region 203 and the electrode plate 204, is usually used in fabricating the stacked DRAM. The recipe etches silicon dioxide and silicon nitride, whereas it does not etch poly silicon. Thus, if the silicon nitride layer 205 on first poly gate electrode 201 is too thick, when fabricating the contact, the first poly gate electrode 201 may be open circuited or the bit line 202 and electrode plate 204 may be etched through.
It is obvious that the technique used to form the borderless contact etching is a critical process due to the thickness of the silicon nitride on the gate poly silicon. To overcome the disadvantage of the technique mentioned above, the structure of the gate electrode must be improved to avoid the affect of the thickness of the silicon nitride on the gate poly silicon.